1. Field of the Invention:
The present invention relates to a semiconductor device having, on a principal surface of a substrate, a plurality of functional blocks each having a function to hold either a voltage determined by a current supplied from a current source or a voltage supplied from a voltage source and to supply a current or a voltage determined by the voltage thus held to an external circuit, and more particularly to a semiconductor device having a layout suitable for use as a driver for a display apparatus, and a display apparatus employing such a semiconductor device.
2. Description of the Related Art
Semiconductor devices having a matrix of current-driven load elements such as OLED (Organic Light-Emitting Diodes) typified by organic EL (Electro Luminescent) elements employ driving semiconductor devices for supplying currents to drive those current-driven load elements. The driving semiconductor devices have a plurality of functional blocks having a function to hold voltages corresponding to currents to flow through the OLED elements and a function to supply currents according to the voltages that are held.
Heretofore, there has been disclosed a display apparatus having a driving semiconductor device for inputting either gradation currents equal to gradation currents to flow through OLED elements or gradation currents proportional thereto to functional blocks, as shown in A. Yumoto, et al., “Pixel-Driving Methods for Large-Sized Poly-SiAM-OLED displays”, IDW '01, 1395-1398 pages.
The driving semiconductor device serves as a current-program-type data line driver, and has m circuit blocks for holding voltages corresponding to gradation currents supplied from an external circuit and providing current determined by the voltages that are held to 3 m data lines. A display apparatus includes a display unit having m pixels each comprising R (red), G (green), and B (blue) sub pixels, per horizontal (scanning) line. A single data line is connected to each of the sub pixels.
FIG. 1 of the accompanying drawings is a circuit diagram of an ith circuit block for providing currents to three data lines that are connected to an ith pixel on one horizontal line, where i represents a positive integer satisfying i≦m. The circuit block has three pairs of a current copier current output circuit (hereinafter referred to as “cell A”) comprising four transistors Tr101A through Tr104A in the form of N-channel FETs and a single holding capacitor C101, and a current copier current output circuit (hereinafter referred to as “cell B”) comprising four transistors Tr101B through Tr104B in the form of N-channel FETs and a single holding capacitor C101. The three pairs of current output circuits have respective output terminals, which are successively arranged from left to right in FIG. 1, electrically connected respectively to data lines that are connected to R, G, and B sub pixels of the ith pixel. Each of cells A, B serves as a minimum functional block. Transistors Tr102A, Tr102B of cells A, B have respective drains connected to a signal line which is supplied with gradation current lini. Transistors Tr104A, Tr104B have respective gates supplied with respective data enable signals DEA, DEB. One of data enable signals DEA, DEB is of a high level and the other of a low level, and they are reversed each time a horizontal line in the display unit is selected.
FIG. 2 of the accompanying drawings is a timing chart which is illustrative of operation of the circuit clock shown in FIG. 1. In a horizontal period where data enable signal DEA is of a low level and data enable signal DEB is of a high level (horizontal period A in FIG. 2), cells A are supplied with gradation current lini in response to storage timing signals MARi, MAGi, MABi. Specifically, storage timing signal MARi goes high at first, and gradation current lini is supplied which corresponds to a current to pass through the OLED element of ith R sub pixel on a horizontal line next the horizontal line that is being selected. In cell A corresponding to R sub pixel, since transistors Tr102A, Tr103A are turned on, gradation current lini flows into holding capacitor C101, charging holding capacitor C101. In a stable state, holding capacitor C101 holds a voltage between the gate and source of transistor Tr102A (across holding capacitor C101) for passing gradation current lini between the source and drain of transistor Tr102A. When the stable state is reached, storage timing signal MARi goes low, and at the same time storage timing signal MAGi goes high. As with cell A corresponding to R sub pixel, a voltage is held between the source and drain of transistor Tr101A of cell A corresponding to G sub pixel. Then, a voltage is similarly held between the source and drain of transistor Tr101A of cell A corresponding to B sub pixel.
Such a process of holding a voltage is performed in the same horizontal period from the first circuit block to the mth circuit block. At this time, storage timing signals MBRi, MBGi, MbBi that are applied to the gates of transistors Tr102B, Tr103B of cell B are of a low level.
Since transistors Tr102B, Tr103B are turned off, therefore, no gradation current flows into cell B. As transistor Tr101B is turned on, currents IRi, IGi, IBi (i=1, 2, . . . , m) corresponding to voltages held by holding capacitors C101 of cells B from the first circuit block to the mth circuit block in the preceding frame are supplied to the data lines, energizing the OLED elements of the sub pixels on a horizontal line which are connected to the data lines.
In a next horizontal period (horizontal period B in FIG. 2), data enable signal DEA goes high and data enable signal DEB goes low, and transistors Tr101A supply the data lines with currents according to the voltages held in the preceding horizontal period. At the same time, as with transistor Tr101A in the preceding horizontal period, transistors Tr101B hold voltages corresponding to currents to pass through the OLED elements on a horizontal line to be selected next.
In this manner, the supply of currents corresponding to voltages held by transistors Tr101B or Tr101A to the data lines in the preceding horizontal period and the holding of voltages corresponding to currents to be supplied to the data lines in the next horizontal period in transistors Tr101A or Tr101B are switched between cell A and cell B in every horizontal period for thereby displaying information on the display unit.
Driving semiconductor devices such as the above current-program-type data line driver and source drivers for driving liquid crystal display apparatus include analog circuits such as current copier current output circuits and DACs (Digital-to-Analog Converters). The layout of these analog circuits are required to keep the layout area prevented from increasing and also to increase the accuracy, and often incorporate a mirror configuration.
FIG. 3 of the accompanying drawings shows a conventionally designed layout of the circuit block of the current-program-type data line driver shown in FIG. 1. The semiconductor device in the layout shown in FIG. 3 is fabricated on a glass substrate of thin-film transistors made of low-temperature poly-Si (polycrystalline Silicon). The semiconductor device has a first interconnect layer and a second interconnect layer. The first interconnect layer includes interconnects for supplying storage timing signals and data enable signals to the cells, and the second interconnect layer includes interconnects for supplying gradation currents and GND interconnects.
The layout of circuit block 201 shown in FIG. 3 resides in that two cells A, B of the same structure are arranged in a mirror configuration as a current copier current output circuit pair with respect to each data line. Each of areas including transistors and holding capacitors C101 is also arranged in a mirror configuration. These arrangements are effective to reduce variations and errors due to layout differences and increase operational accuracy.
By arranging current copier current output circuit pairs connected to data lines that correspond to successive R, G, B sub pixels in mirror-reversed layouts, adjacent current copier current output circuits that are connected to different data lines can share data enable signals DEA, DEB.
Therefore, a single circuit block requires only four data enable signal lines, making it possible to reduce the layout area, although it would require two data enable signal lines for each current copier current output circuit pair and hence a total of 6 data enable signal lines if not designed in a mirror-reversed layout.
If gradation current lini is supplied from a source-type current source, then currents IRi, IGi, IBi supplied to the data lines are actually currents drawn from the data lines to the source of transistor Tr4A or Tr4B. Depending on the circuit arrangement, currents are discharged to the data lines or drawn from the data lines. In any case, the expression that currents are supplied to the data lines will be used below.
The conventional semiconductor device described above has suffered the following problems:
The first problem is that the conventional mirror layout poses limitations on efforts to increase the accuracy of the gradation current and achieve more gradations with the gradation current. With the mirror layout, cells A, B connected to the same data line, including interconnects, are arranged symmetrically with respect to their central axis, but are not arranged identically as viewed from the same direction in which cells A, B are arrayed. Therefore, if the manufacturing process that is used is directional, e.g., if the process characteristics are a function of the position between two adjacent cells A, B, then the operational characteristics are highly likely to differ between such two adjacent cells A, B.
For example, in the above conventional example, the left current copier current output circuit (cell A or cell B) of the current copier current output circuit pair shown in FIG. 3 has one interconnect on the left of holding capacitor C101 and two interconnects on the right of holding capacitor C101, whereas the right current copier current output circuit (cell B or cell A) has two interconnects on the left of holding capacitor C101 and one interconnect on the right of holding capacitor C101. Therefore, if the manufacturing process is directional, then the capacitances between the two adjacent cells suffer process-dependent characteristic variations, resulting in a reduction in the output accuracy.
Furthermore, if interconnects are shared by mirror-reversed circuits in the above conventional design, then the relationship between the cells and the interconnects may vary between the cells. For example, with the circuit block 201 shown in FIG. 3, a cell in the central area has two interconnects on one side thereof and a single interconnect on the other side thereof, and a cell in each of the left and right ends has two interconnects on each side thereof. Such a layout difference will appear as a noise difference, for example, tending to cause a variation between currents supplied to the cells.
The second problem is that the currents supplied by the cells have their accuracy lowered because no full consideration is given to attempts to suppress the effect of noise. If parasitic capacitances such as a capacitance between adjacent interconnects and a capacitance between interconnect layers are not sufficiently taken into account, then when a signal is transmitted to an interconnect, the effect of the noise appears as noise in another interconnect or a capacitor, tending to lower the accuracy of the current supplied from the cell.